Software Controlled Cache Coherence in Shared-Memory Multiprocessors

During the last few years many different memory consistency protocols have been proposed. These range from strong models like sequential consistency or processor consistency to weak ones like weak ordering, release consistency and SCNF. Implementations of these protocols are usually transparent to application programs: They try to hide as much detail as possible, usually leaving 'well behaved' applications with a sequential consistent memory view. There are two reasons why a different approach to memory consistency is chosen in this paper. On one hand this transparency of protocols imposes a limit on the amount of information about data access categories that can be given by applications. More information could reduce coherence overhead substantially. On the other hand sequential consistency is not the only feasible programming model for writing parallel programs. Most applications do not rely on the strong limitations given by it, because they synchronize to access shared data. We the..