AbstractIn this paper we describe a network invariant for all configurations of the Futurebus+ Cache Coherence Protocol. The network invariant was computed with PAX and verified by a model checker. Using this invariant we are able to prove a specification of cache coherence correct for an arbitrary number of components on a single bus of the system. This specification includes a progress property not proven yet. We show how the result for the single bus system can be extended to tree-shaped systems. This is, as far as we know, the first uniform proof of the protocol with multiple data-buses
We combine compositional reasoning and reachability analysis to formally verify the safety of a rece...
Many electrical engineers would agree that, had it not been for link-level acknowledgements, the eva...
Abstract. This paper presents a case study of the application of the knowledge-based approach to con...
AbstractIn this paper we describe a network invariant for all configurations of the Futurebus+ Cache...
This paper presents a case study for automatic verifi-cation using the Communicating Sequential Proc...
Abstract Performance modelling and verification are vital steps in the development cycle of any cach...
Thesis (Ph. D.)--University of Washington, 1987Shared-memory multiprocessors offer increased computa...
Cache coherency is one of the major issues in multicore systems. Formal methods, in particular model...
Abstract—We propose an architectural design methodology for designing formally verifiable cache cohe...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
This thesis presents a new cache coherence protocol for shared bus multicache systems, and addresses...
In this paper we present a cache coherence protocol for multistage interconnection network (MIN)-bas...
technical reportWe address the problem of developing efficient cache coherence protocols for use in ...
International audienceWe present a formal model built for verification of the hardware Tera-Scale AR...
The use of private caches in a multiprocessor system causes inconsistency of the shared data among t...
We combine compositional reasoning and reachability analysis to formally verify the safety of a rece...
Many electrical engineers would agree that, had it not been for link-level acknowledgements, the eva...
Abstract. This paper presents a case study of the application of the knowledge-based approach to con...
AbstractIn this paper we describe a network invariant for all configurations of the Futurebus+ Cache...
This paper presents a case study for automatic verifi-cation using the Communicating Sequential Proc...
Abstract Performance modelling and verification are vital steps in the development cycle of any cach...
Thesis (Ph. D.)--University of Washington, 1987Shared-memory multiprocessors offer increased computa...
Cache coherency is one of the major issues in multicore systems. Formal methods, in particular model...
Abstract—We propose an architectural design methodology for designing formally verifiable cache cohe...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
This thesis presents a new cache coherence protocol for shared bus multicache systems, and addresses...
In this paper we present a cache coherence protocol for multistage interconnection network (MIN)-bas...
technical reportWe address the problem of developing efficient cache coherence protocols for use in ...
International audienceWe present a formal model built for verification of the hardware Tera-Scale AR...
The use of private caches in a multiprocessor system causes inconsistency of the shared data among t...
We combine compositional reasoning and reachability analysis to formally verify the safety of a rece...
Many electrical engineers would agree that, had it not been for link-level acknowledgements, the eva...
Abstract. This paper presents a case study of the application of the knowledge-based approach to con...