Add to ORKGThis paper presents a case study for automatic verifi-cation using the Communicating Sequential Processes formalism. The case study concerns the Futurebus+ cache coherency standard; we develop a formal model of the protocol and perform some verification tasks upon it. In the process of doing so, we extend the previous solution by developing a formal specification of cache coherence that is suitable for the verification of both directory and snooping based cache coherence protocols.
This paper describes two projects to formally specify and verify cache-coherence protocols for multi...
Abstract—We propose an architectural design methodology for designing formally verifiable cache cohe...
With the maturing of computer-aided verification technology, there is an emerging opportunity to dev...
AbstractIn this paper we describe a network invariant for all configurations of the Futurebus+ Cache...
This paper describes our experience applyingformal verification to the cache coherence protocol of t...
Abstract Performance modelling and verification are vital steps in the development cycle of any cach...
Abstract. This paper presents a case study of the application of the knowledge-based approach to con...
Computers have brought us inestimable convenience in recent years. We have become dependent on them ...
Cache coherency is one of the major issues in multicore systems. Formal methods, in particular model...
AbstractModel checking is a proven successful technology for verifying hardware. It works, however, ...
Model checking is a proven successful technology for verifying hardware. It works, however, on only ...
Computer architects have often used trace-driven simulations to evaluate the performance of new arch...
This invited paper argues that to facilitate formal verification, multiprocessor systems should (1) ...
A cache coherence protocol is a set of rules, which cache controllers in a system with multiple cach...
We describe a technique for verifying that a hardware design correctly implements a protocol. The ap...
This paper describes two projects to formally specify and verify cache-coherence protocols for multi...
Abstract—We propose an architectural design methodology for designing formally verifiable cache cohe...
With the maturing of computer-aided verification technology, there is an emerging opportunity to dev...
AbstractIn this paper we describe a network invariant for all configurations of the Futurebus+ Cache...
This paper describes our experience applyingformal verification to the cache coherence protocol of t...
Abstract Performance modelling and verification are vital steps in the development cycle of any cach...
Abstract. This paper presents a case study of the application of the knowledge-based approach to con...
Computers have brought us inestimable convenience in recent years. We have become dependent on them ...
Cache coherency is one of the major issues in multicore systems. Formal methods, in particular model...
AbstractModel checking is a proven successful technology for verifying hardware. It works, however, ...
Model checking is a proven successful technology for verifying hardware. It works, however, on only ...
Computer architects have often used trace-driven simulations to evaluate the performance of new arch...
This invited paper argues that to facilitate formal verification, multiprocessor systems should (1) ...
A cache coherence protocol is a set of rules, which cache controllers in a system with multiple cach...
We describe a technique for verifying that a hardware design correctly implements a protocol. The ap...
This paper describes two projects to formally specify and verify cache-coherence protocols for multi...
Abstract—We propose an architectural design methodology for designing formally verifiable cache cohe...
With the maturing of computer-aided verification technology, there is an emerging opportunity to dev...