Trim Algorithm Analysis

Selling integrated circuits (IC) in consumer markets places a high emphasis on cost. Average selling prices (ASP) tend to be low due to customer price pressure and competition. One of the largest costs associated with manufacturing ICs is the subsequent test cost. The test time for complex chips is approaching 50% of total package-device cost.[1] This is broken down into hardware utilization time and man-hours. The more time that is spent testing one product means less time is available for testing other products. Getting capital expenditures approval to buy more test equipment is generally a hard sell, and even if approved the long lead times prove to be not convenient for alleviating test bottlenecks. One of the best ways to improve test costs is to reduce the test time per unit. Faster unit testing allows the existing hardware to test more products given the same amount of time. The first place to investigate potential savings is to start at the functional level. Semiconductor companies produce an electrical table highlighting the specifications of the part. The industry standard is to break down these specifications into three categories: minimum, maximum, and typical values. Specifications that fall under the heading of minimum or maximum are required to be guaranteed either by the design of the part or by production testing. This paper will discuss an analysis method designed to improve one of the more time-consuming tests, one-time programmable (OTP) trims