Statistical modeling of fault coverage and optimizations in VLSI testing

As the complexity of Very Large Scale Integrated (VLSI) devices increases, so does the cost of testing the VLSI devices. VLSI testing has to be cost effective to meet the challenges of the technology advance. Test cost is incurred during both the test-preparation and test-application phases. In this thesis we address test cost issues in these two phases. First we present a simple, accurate fault coverage model, which can help to reduce the cost of test preparation; then we propose test optimization methods which can help reduce the cost of the test application process. Previous models of fault coverage analysis are either too simplistic or require full fault simulation. We present a new probabilistic fault coverage model that is accurate, simple, predictive, and easily integrated with the normal design flow of built-in self-test circuits. The parameters of the model are determined by fitting the fault simulation data obtained on an initial segment of the random test. A cost-based analysis finds the point at which to stop fault simulation, determine the parameters, and estimate fault coverage for longer test lengths. Experimental results on benchmark circuits demonstrate the effectiveness of this approach in making accurate predictions at a low computational cost. We examine potential methods that may reduce the cost of test application. We first show that by permuting test vectors based on normal test data, we can improve the test efficiency by over 10%. Algorithms for test reordering are developed with the goal of minimizing the test cost. Best and worst case bounds are established for the performance of a reordered sequence compared to the original sequence of test application. Secondly, the risk of dropping test vectors that do not fail any chips is analyzed against the cost benefits. The same idea is used to optimize the test plans by changing the order of different tests