An improved VLSI test economics analysis system

[[abstract]]Managers used to consider design for testability (DFT) as an overhead in development and produc- tion rather than an aid. We take a full considera- tion on the relation between DFT methodologies and cost/revenue models, and show that DFT may actu- ally help engineers to shorten the total time needed in product development, which leads to lower man- power cost and shorter time to market, and therefore results in more revenue through out the product's life time. Base on this, economic models are developed to model the cost and revenue of a VLSI product. Also, an improved WWW-based VLSI test strategy plan- ning system|the Evaluation System for TEst Engi- neering Methodologies (ESTEEM)|has been devel- oped for our models. We apply our system to a case and obtain the threshold volume where the cost of de- sign with DFT is lower than the design without DFT.[[fileno]]2030108030165[[department]]電機工程學