In Electronic System Design By

As the multiprocessors scale beyond the limits of a few tens of processors, we must look beyond the traditional methods of synchronization to minimize serialization and achieve high degrees of parallelism required to utilize large machines. Since synchronization is a major performance parameter for such a level of parallelism, efficient support for synchronization is therefore a major issue. By allowing synchronization at the level of smallest unit of memory, fine-grain synchronization achieves this goal and it has significant performance as compare to traditional coarse-grain synchronization. It has already been proved that hardware support for fine-grain synchronization provides significant improvement in the performance over coarse-grain synchronization mechanisms like barriers. As demonstrated by the machine MIT Alewife, integrated support for fine-grain synchronization can have significant performance benefits over coarse-grain. The major goal of research is to evaluate the efficient way to support the fine-grain synchronization mechanisms in multiprocessors. The best way of approaching to this goal is based on the efficient combination of fine-grain synchronization with cach