Fine-grain parallelism on sequential processors

Graduation date: 1995There seems to be a consensus that future Massively Parallel Architectures\ud will consist of a number nodes, or processors, interconnected by high-speed network.\ud Using a von Neumann style of processing within the node of a multiprocessor system\ud has its performance limited by the constraints imposed by the control-flow execution\ud model. Although the conventional control-flow model offers high performance on\ud sequential execution which exhibits good locality, switching between threads and synchronization\ud among threads causes substantial overhead. On the other hand, dataflow\ud architectures support rapid context switching and efficient synchronization but require\ud extensive hardware and do not use high-speed registers.\ud There have been a number of architectures proposed to combine the instruction-level\ud context switching capability with sequential scheduling. One such architecture\ud is Threaded Abstract Machine (TAM), which supports fine-grain interleaving of multiple\ud threads by an appropriate compilation strategy rather than through elaborate hardware.\ud Experiments on TAM have already shown that it is possible to implement the dataflow\ud execution model on conventional architectures and obtain reasonable performance.\ud These studies also show a basic mismatch between the requirements for fine-grain\ud parallelism and the underlying architecture and considerable improvement is possible through hardware support.\ud This thesis presents two design modifications to efficiently support fine-grain parallelism. First, a modification to the instruction set architecture is proposed to reduce the cost involved in scheduling and synchronization. The hardware modifications are kept to a minimum so as to not disturb the functionality of a conventional RISC processor. Second, a separate coprocessor is utilized to handle messages. Atomicity and message handling are handled efficiently, without compromising per-processor performance and system integrity. Clock cycles per TAM instruction is used as a measure to study the effectiveness of these changes