Performance and Power-Consumption Implication of Fine-Grained Synchronization in Multiprocessors

It has been already verified that hardware-supported fine-grain synchronization provides a significant performance improvement over coarse-grained synchronization mechanisms, such as barriers. Support for fine-grain synchronization on individual data items becomes notably important in order to implement thread-level parallelism more efficiently. One of the major goals of this project is to propose a new efficient way to support fine-grain synchronization mechanisms in multiprocessors. This novel idea is based on the efficient combination of fine-grain synchronization with cache coherence and instruction level parallelism. Both snoopy and directory-based cache coherence protocols have been studied. The work includes the definition of the complete set of synchronizing memory instructions as well as the architecture of the full/empty tagged shared memory that provides support for these operations. A detailed model based on a shared memory multiprocessor is presented and systematically described. To achieve this, an existing execution-driven simulator, namely RSIM, has been appropriately adapted. The simulation environment is designed for verification and performance evaluation of the proposed solutions