Efficient fine-grain synchronization on a multi-core chip architecture: A fresh look

Multi-core chip architectures are becoming mainstream, permitting increasing on-chip paral-lelism through hardware support for multithreading. Fine-grain synchronization is essential to the effective utilization of the capacity provided by future high-performance multi-core architectures. However, there are also new challenges realizing such fine-grain synchronization in large-scale multi-core chip architectures – such as the IBM Cyclops-64 chip that contains more than 100 pro-cessing cores and employs a memory organization with explicitly addressable memory segments instead of data cache. This paper presents a fresh look at the challenges and proposes a scalable solution for fine-grain synchronization that efficiently enforces mutual exclusion and read-after-write data-dependencies between concurrent threads. Using the Cyclops-64 chip architecture as a case study, we illustrate how to use a small Synchronization State Buffer (SSB) associated with each memory bank to acceler-ate the fine-grain synchronization by recording and managing the states of frequently synchronized data units with modest hardware extensions. We demonstrate the effectiveness and efficiency of the proposed solution