Exploring alternatives to hardware support for fine-grain synchronization

As we prepare for the extreme-scale era of computing, communication overhead and synchronization between cores will soon become extremely important. In this work we study three different methods of support for fine-grain synchronization. Fine-grain synchronization allows a task to be broken up into very small units, improving load balancing and reducing lock contention. The different methods include hardware support for full/empty bits, compare-and-swap (CAS) emulation of full/empty bits, and dual CAS operations. Roger Golliver’s single CAS implementation is a novel method which chooses a bit pattern to represent an “empty” full/empty bit state. The primary concerns are hardware overhead, efficiency of the synchronization, and energy wasted while spinning. We have tested the methods on a set of four different highly parallel algorithms on up to 32 cores. Our results show that fine-grain synchronization can have significant performance benefits, and emulation through CAS can do just as well as hardware-supported full/empty bits in many cases. We had much difficulty finding suitable algorithms that use fine-grain synchronization in a meaningful way, and among those that did use fine-grain synchronization meaningfully, there were limited cases where hardware support had a significant advantage over emulation through CAS. Given these results, we find it difficult to justify including full/empty bits in an extreme-scale design