Instruction Issue Logic for Pipelined Supercomputers

Basic pr inc ip les and des ign t radeof fs for cont ro l ol p ipe l ined processors are f i rst d iscussed. We concent ra te on reg is ter- reg is ter a rch i tec tures l ike the GRAY-1 where pipel ine cont ro l logic is local ized to one or two pipel ine s tages and is re fer red to as " ins t ruct ion issue logic". Design tradeoffs are exp lored by giving des igns for a var ie ty of ins t ruct ion issue methods that represent a range of complex i ty and sophist icat ion. These vary f rom the or ig inal CRAY-1 issue logic to a vers ion of Tomasulo 's a lgor i thm, f i rst used in the IBM 360/91 f loating point unit. Also s tud ied are Thornton 's "scoreboard " algo-r i thm used on the CDC 8600 and an a lgor i thm we have devised. To provide a s tandard for compar ison, all the issue methods are used to imp lement the GRAY-1 sca lar a rch i tec ture. Then, us ing a s imulat ion model and th