HIS: an instruction issue mechanism for hyperscalar processors

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item.Includes bibliographical references.A dynamic instruction issue scheme using multiple independent threads is presented. The proposed scheme works out a compromise between processor throughput and resource utilization. This is accomplished by enhancing the instruction issue rate by providing multiple functional units and by improving resource utilization by supporting multiple instruction threads. Pipeline stalls are decreased by diminishing the effect of control instructions and hardware resource sharing is provided. A dual-threaded hyperscalar processor architecture developed to test this instruction issue scheme is described. The simulation models developed to evaluate and compare the performance of this scheme with an analogous single-threaded processor and a single instruction issue pipelined processor are explained. Simulation results show a substantial increase in processor throughput and functional unit utilization when this scheme is used