Task and instruction scheduling in parallel multithreaded processors

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to digital@library.tamu.edu, referencing the URI of the item.Includes bibliographical references: p. 57-59.Issued also on microfiche from Lange Micrographics.Parallel muitithreading is a technique to execute parallel programs on a multithreaded superscalar processor. It enhances instruction throughput in a processor by combining program parallelism with the strong features of superscalar and multithreaded architectures: the multiple-instruction-issue ability of a superscalar processor, and the latency-hiding feature of multithreaded architectures. In such processors, several threads issue instructions to a superscalar processors multiple functional units every cycle. A new prioritizatioin, technique based on a critical path based analysis of program graphs is shown to enhance instruction throughput significantly by scheduling the best threads (or tasks) from a parallel Program on to the processor Pipelines, and by issuing the best instructions from the fetched threads to the multiple functional units of the processor. Simulation-based comparisons show that our task and instruction scheduling techniques Yield an instruction throughput UP to 20% better than previously proposed prioritization techniques that employ heuristics based on considerations other than a critical path analysis of the program graph. Our simulations employ Parallel applications chosen carefully to reflect diverse program behavior. Our results suggest the use Of superscalar multithreaded processors in order to Perform efficient Parallel processing