Static instruction scheduling for dynamic issue processors

This thesis presents a novel approach to the instruction scheduling problem for dynamic issue processors. Our approach aims at generating an instruction sequence with a low register pressure and a high level of Instruction-Level Parallelism (ILP) exploitable by the dynamic issue mechanism of the processor. Our objective is to improve the performance of the program by taking advantage of the out-of-order execution and register renaming mechanisms of the processor to reduce the amount of spill code introduced by the register allocator.Our approach uses a traditional ILP scheduler to generate an initial schedule for the program, and then reorders its instructions to reduce the register pressure of the program. This reordering is performed carefully. to ensure that the dynamic issue mechanism of the processor is able to exploit from the reordered sequence as much parallelism as available on the original schedule.We have proposed an approximate method to determine, for a given instruction sequence and a given instruction schedule, whether a particular dynamic issue superscalar processor can exploit from the sequence as much ILP as present in the schedule. (Abstract shortened by UMI.