Issue logic for a 600-MHz out-of-order execution microprocessor

Abstract—The logic and circuits are presented for a 20-entry instruction queue which scoreboards 80 registers and issues four instructions per cycle in a 600-MHz microprocessor. The request logic and arbiter circuits that control integer execution are described in addition to a novel compaction scheme that maintains temporal order in the queue. The issue logic data path is implemented in 141 000 transistors, occupying 10 mm2 in a 0.35-m CMOS process. Index Terms—CMOS digital integrated circuit, issue, micro-processor, out-of-order, queue. I