Performance, Design

A major consumer of microprocessor power is the issue queue. Several microprocessors, including the Alpha 21264 and POWER4 use a compacting latch-based issue queue design which has the ad-vantage of simplicity of design and verification. The disadvantage of this structure, however, is its high power dissipation. In this paper, we explore different issue queue power optimiza-tion techniques that vary not only in their performance and power characteristics, but in how much they deviate from the baseline im-plementation. By developing and comparing techniques that build incrementally on the baseline design, as well as those that achieve higher power savings through a more significant redesign effort, we quantify the extra benefit the higher design cost techniques provide over their more straightforward counterparts