Single issue instruction dispatcher based on Tomasulo???s algorithm

Includes bibliographical references (page 27)In order to achieve maximum throughput and efficiency, today???s processors employ various techniques and algorithms. Some of these would involve implementing multi-level cache, multiprocessor systems or exploring parallelism within instructions. Tomasulo???s algorithm by Robert Tomasulo has proved to be a major technique of exploiting the possibility of parallel and out-of-order execution of instructions. This project involves HDL implementation of Tomasulo???s algorithm on Xilinx ISE 14.2 using Verilog HDL. The algorithm consists of a scheduler which is the heart of the system responsible for eliminating structural and data hazards to allow efficient instruction execution