Double patterning lithography appears a likely candidate to bridge the gap between water-based immersion lithography and EUV. A double patterning process is discussed for 30nm half-pitch interconnect structures, using 1.2 NA immersion lithography combined with the Motif (TM) CD shrink technique. An adjusted OPC calculation is required to model the proximity effects of the Motif shrink technique and subsequent metal hard mask (MHM) etch, on top of the lithography based proximity effects. The litho-etch-litho-etch approach is selected to pattern a TiN metal hard mask. This mask is then used to etch the low-k dielectric. The various process steps and challenges encountered are discussed, with the feasibility of this approach demonstrated by su...
The development of double patterning processes/schemes are widely in progress for 2x nm node and bey...
Due to the inherent limitation from overlay shift control, the punch-through scheme coupled with via...
Moore's law has been guiding the semiconductor industry for four decades. Lithography is the ke...
Double patterning lithography appears a likely candidate to bridge the gap between water-based immer...
Double patterning lithography appears a likely candidate to bridge the gap between water-based immer...
Double patterning lithography appears a likely candidate to bridge the gap between water-based immer...
A double patterning (DP) process is discussed for 50nm half pitch interconnects, using a litho-etch-...
A double patterning (DP) process is discussed for 50nm half pitch interconnects, using a litho-etch-...
A double patterning (DP) process is discussed for 50nm half pitch interconnects, using a litho-etch-...
Several options are being explored to extend device scaling towards and beyond the 32nm Half Pitch (...
In this paper, metal hard-ma.sk-based patterning schemes are proposed to pattern 30/30 nm line/space...
Pattern reduction has generated much interest in development effective methods of reducing the featu...
Pattern reduction has generated much interest in development effective methods of reducing the featu...
The goal of this project was to successfully demonstrate a double patterning technique using equipme...
The goal of this project was to successfully demonstrate a double patterning technique using equipme...
The development of double patterning processes/schemes are widely in progress for 2x nm node and bey...
Due to the inherent limitation from overlay shift control, the punch-through scheme coupled with via...
Moore's law has been guiding the semiconductor industry for four decades. Lithography is the ke...
Double patterning lithography appears a likely candidate to bridge the gap between water-based immer...
Double patterning lithography appears a likely candidate to bridge the gap between water-based immer...
Double patterning lithography appears a likely candidate to bridge the gap between water-based immer...
A double patterning (DP) process is discussed for 50nm half pitch interconnects, using a litho-etch-...
A double patterning (DP) process is discussed for 50nm half pitch interconnects, using a litho-etch-...
A double patterning (DP) process is discussed for 50nm half pitch interconnects, using a litho-etch-...
Several options are being explored to extend device scaling towards and beyond the 32nm Half Pitch (...
In this paper, metal hard-ma.sk-based patterning schemes are proposed to pattern 30/30 nm line/space...
Pattern reduction has generated much interest in development effective methods of reducing the featu...
Pattern reduction has generated much interest in development effective methods of reducing the featu...
The goal of this project was to successfully demonstrate a double patterning technique using equipme...
The goal of this project was to successfully demonstrate a double patterning technique using equipme...
The development of double patterning processes/schemes are widely in progress for 2x nm node and bey...
Due to the inherent limitation from overlay shift control, the punch-through scheme coupled with via...
Moore's law has been guiding the semiconductor industry for four decades. Lithography is the ke...