In this paper, we describe distributed algorithms for combinational fault simulation assuming the classical stuck-at fault model. Our algorithms have been implemented on a network of Sun workstations under the Parallel Virtual Machine (PVM) environment. Two techniques are used for subdividing work among processors – test set partition and fault set partition. The sequential algorithm for fault simulation, used on individual nodes of the network, is based on a novel path compression technique proposed in this paper. We describe experimental results on a number of ISCAS′85 benchmark circuits
This dissertation describes a new simulation technique for an automatic test generation system, SCIR...
Current and future multicore architectures can significantly accelerate the performance of test auto...
We consider issues of fault tolerance for distributed computing systems at two levels of system desi...
In this paper, we describe distributed algorithms for combinational fault simulation assuming the cl...
To explore the potential speedup to be obtained through parallelism, a mathematical model for the pe...
Distributed computing attempts to aggregate different computing resources available in enterprises a...
We propose a new method to speed up stuck-at fault simulation for sequential circuits. The method co...
110 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1997.All implementations were done...
In the past decade, the use of distributed algorithms to model simulations is considerably increased...
An efficient method of parallel fault simulation for combinational circuits is proposed. The method ...
Trace-based methods have been shown to be more effective than traditional fault simulation methods. ...
© 2017 IEEE. Fault simulation is very important task for testing and fault diagnostics based on the ...
Abstract We present a new multiprocessor sequential circuit fault simulator, Zamlog, b ased on a nov...
With increase in complexity of digital circuits, it has become extremely important to detect faults ...
Abstract Embedded parallel and distributed computing systems for real-time applications are becoming...
This dissertation describes a new simulation technique for an automatic test generation system, SCIR...
Current and future multicore architectures can significantly accelerate the performance of test auto...
We consider issues of fault tolerance for distributed computing systems at two levels of system desi...
In this paper, we describe distributed algorithms for combinational fault simulation assuming the cl...
To explore the potential speedup to be obtained through parallelism, a mathematical model for the pe...
Distributed computing attempts to aggregate different computing resources available in enterprises a...
We propose a new method to speed up stuck-at fault simulation for sequential circuits. The method co...
110 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1997.All implementations were done...
In the past decade, the use of distributed algorithms to model simulations is considerably increased...
An efficient method of parallel fault simulation for combinational circuits is proposed. The method ...
Trace-based methods have been shown to be more effective than traditional fault simulation methods. ...
© 2017 IEEE. Fault simulation is very important task for testing and fault diagnostics based on the ...
Abstract We present a new multiprocessor sequential circuit fault simulator, Zamlog, b ased on a nov...
With increase in complexity of digital circuits, it has become extremely important to detect faults ...
Abstract Embedded parallel and distributed computing systems for real-time applications are becoming...
This dissertation describes a new simulation technique for an automatic test generation system, SCIR...
Current and future multicore architectures can significantly accelerate the performance of test auto...
We consider issues of fault tolerance for distributed computing systems at two levels of system desi...