[[abstract]]In recent years, the power devices become more and more important due to the big demands for liquid crystal display (LCD), electrical plasma display, LED, and communication products. It is a future trend that power devices and low voltage will be integrated on the same chip; however, one of very important power devices is LDMOS. It is often unable to simulate devices with special layouts such as Racetracks and Fingers, and so in this thesis it focuses on 3D simulations of power device LDMOS by using Sentaurus tool. The 3D simulation results of power device LDMOS of Power Device shows serious Current Crowding Effects which the traditional 2D simulation is unable to achieve. There are two methods to reduce Current Crowding Effect...
[[abstract]]In recent years, because new display and communication products bring forth and substitu...
A linearly graded doping drift region structure, a novel lateral voltage-sustained layer used for im...
The physical mechanisms specific for 40 V LDMOS power transistors under ESD stress (gate grounded/co...
[[abstract]]Accompanied by the development of the semiconductor industry, high power de-vices are of...
the frequently used method to design a high voltage lateral devices with high break down voltage and...
An in-depth comprehension of the electrical behaviour of a RESURF LDMOS is given. Avalanche breakdow...
We present drain and source-centric design optimizations of a linear P-top and dual-channel conducti...
ABSTRACT The Lateral Double-Diffused Metal-Oxide-Semiconductor Field Effect Transistor (LDMOSFET or ...
[[abstract]]In recent years, because of flat-panel displays and communications products replacing ol...
[[abstract]]In this thesis, a novel 800V multiple RESURF lateral double-diffused MOS (LDMOS) transis...
[[abstract]]We present drain and source-centric design optimizations of a linear P-top and dual-chan...
[[abstract]]Dr. Gene Sheu, Nithin,D P. 2010. Method of making High-Voltage Linear P-Buried Rings LDM...
[[abstract]]n this paper, we have simulated and analyzed the effect of fingers, device-width and mai...
A new RESURF LDMOS transistor using a linearly varying surface-implanted doped (LVD) n(-) layer is r...
[[abstract]]In this work, a novel multiple RESURF P-top rings LDMOS with shallow trench isolation (S...
[[abstract]]In recent years, because new display and communication products bring forth and substitu...
A linearly graded doping drift region structure, a novel lateral voltage-sustained layer used for im...
The physical mechanisms specific for 40 V LDMOS power transistors under ESD stress (gate grounded/co...
[[abstract]]Accompanied by the development of the semiconductor industry, high power de-vices are of...
the frequently used method to design a high voltage lateral devices with high break down voltage and...
An in-depth comprehension of the electrical behaviour of a RESURF LDMOS is given. Avalanche breakdow...
We present drain and source-centric design optimizations of a linear P-top and dual-channel conducti...
ABSTRACT The Lateral Double-Diffused Metal-Oxide-Semiconductor Field Effect Transistor (LDMOSFET or ...
[[abstract]]In recent years, because of flat-panel displays and communications products replacing ol...
[[abstract]]In this thesis, a novel 800V multiple RESURF lateral double-diffused MOS (LDMOS) transis...
[[abstract]]We present drain and source-centric design optimizations of a linear P-top and dual-chan...
[[abstract]]Dr. Gene Sheu, Nithin,D P. 2010. Method of making High-Voltage Linear P-Buried Rings LDM...
[[abstract]]n this paper, we have simulated and analyzed the effect of fingers, device-width and mai...
A new RESURF LDMOS transistor using a linearly varying surface-implanted doped (LVD) n(-) layer is r...
[[abstract]]In this work, a novel multiple RESURF P-top rings LDMOS with shallow trench isolation (S...
[[abstract]]In recent years, because new display and communication products bring forth and substitu...
A linearly graded doping drift region structure, a novel lateral voltage-sustained layer used for im...
The physical mechanisms specific for 40 V LDMOS power transistors under ESD stress (gate grounded/co...