VLSI architectures for high-speed motion estimator

[[abstract]]The authors propose a fast hierarchical motion estimation algorithm with competent performance as well as reasonable hardware complexities. Because both the coarse search stage and the fine search stage are similar to the full search method, they modify the array architecture of A. Artieri and F. Jutland (1989) to meet the requirements of respective stages. Their architecture has important characteristics that the processing time is directly proportional to the number of the input pixels of the current frame. Because the architecture of the proposed search algorithm is wholly pipelineable and the input pixels of the coarse search stage can be decimated, the authors' proposed architecture improves the throughput rate about four times of the architecture for full search. Besides, they also take the access time of RAM into consideration in the array architectures design. Thus, this architecture is suitable for HDTV applications[[fileno]]2030101030002[[department]]電機工程學