High performance hardware architectures for a hexagon-based motion estimation algorithm

Abstract—Motion Estimation is the most computationally intensive part of video compression and video enhancement systems. For the recently available high definition frame sizes and high frame rates, the computational complexity of full search motion estimation algorithm is prohibitively high, while the PSNR obtained by fast search algorithms is low. Therefore, in this paper, we propose a hexagon-based motion estimation algorithm and two high performance hardware architectures for implementing this algorithm. The proposed algorithm has lower computational complexity than full search algorithm, and the simulation results showed that the PSNR obtained by this algorithm is better than the PSNR obtained by other fast search algorithms. Both hardware architectures are implemented in VHDL and mapped to Xilinx FPGAs. Both hardware architectures can run at 144 MHz when implemented on an XC3S1200E-5 FPGA, and they can process 25 1920x1080 frames per second for the largest search range (±32, ±16). Various fast search algorithms can be implemented using the first hardware architecture. But, it uses 80 Block RAMs. Only the hexagon-based algorithm proposed in this paper can be efficiently implemented using the second hardware architecture. However, it uses 16 Block RAMs and fits into XC3S1200E-5, a low cost Xilinx Spartan-3E FPGA. In addition, a novel data reuse method is used in the second architecture to reduce the number of internal memory accesses, and it has low control overhead because of its regular data flow. Therefore, it can be used in consumer electronics products. I