VLSI Architecture Design of a High-Speed Motion Estimator for HDTV Application

[[abstract]]In this paper, we propose a hierarchical motion estimation algorithm and develop VLSI architectures with reasonable hardware complexities. Motion estimation is to be conducted in two stages, namely coarse search stage and fine search stage. In both search stages, full search method is applied. Global motions are firstly determined using large reference blocks with large search ranges and subsampling in the first stage. Utilizing the global vectors as an offset in the second step with small blocks and small search ranges the local vectors are found thereafter. Furthermore, a large number of memory accesses are necessary usually. With thoughtful selection of parameters the number of memory accesses can be further reduced, if search windows for neighboring reference windows overlap. Our architecture has important characteristics that the processing time is proportional to the number of the input pixels of the current frame. Because the input pixels of the coarse search stage can be decimated, our proposed architecture reduces both the block size and the search area by four times of the architecture for full search, leading to great reduction of the size of the motion estimator. Thus, this architecture is suitable for HDTV applications.[[fileno]]2030101030054[[department]]電機工程學