Design of a VLIW compute accelerator on the TM-2

grantor: University of TorontoComputationally intensive application programs can be accelerated by a customized computer. Multiple specialized functional units are implemented in FPGAs to speed up the computational kernels in hardware. The design of these machines, can be expensive and time consuming since a specialized compiler and a set of functional units must be designed for each application. [Wan99] introduced a general architecture for customized computers and a compiler called 'PECompiler' which can automatically generate both hardware and software for field-programmable compute accelerators. The parameterized compute accelerator introduced in [Wan99] is completed with the design of the control units. A generic Very Long Instruction Word (VLIW) instruction set is defined for the proposed compute accelerator architecture. A code generator is designed to generate the bit-level instructions for execution on the customized computer. Hardware accelerators are designed and implemented for two application program on the TM-2 based system. It is demonstrated that for these two application programs, the hardware accelerators can provide significant performance improvement over the general-purpose CPU.M.A.Sc