Operating System Interfaces to Reconfigurable Systems Approved by

In this work, a hybrid CPU/accelerator platform, which runs a standard operating system, is proto-typed using an FPGA. The goal is to provide consistent, protected, low overhead interfaces for accelerator developers to target. These interfaces enable software application developers to exploit the parallel pro-cessing power of hardware accelerators and reconfigurable computing. Furthermore, we aim to decouple the process of software development from accelerator design in a heterogeneous model of computation. A switchable interconnect accelerator framework is developed to explore what resources should be embedded in future CPU/accelerator systems. We mate our accelerator and application-level inter-faces to provide a seamless platform for developing hardware accelerated applications. Complexity of debugging and development using our framework is lowered by reducing the signal count by over 80%, compared to a stand-alone accelerator design. A hardware accelerated JPEG encoding application serves as a motivating example throughout this work. A computation model is developed to allow standard applications running on our platform to ac-cess reconfigurable accelerators. The applications access accelerators, synthesized in the FPGA fabric, through an operating system layer. Applications running on the CPU interface with the accelerator