RVSingle: A general purpose power efficient RISC-V for FPGAs

With the increasing need for low-cost, power-efficient computing units, RISC-Vas an open-standard Instruction Set Architecture (ISA) is becoming more and more popular in the industry. There are multiple open-source RISC-V soft processors like cva6, VEGA, NOEL-V and more. But those processors have a common problem in that they can only be implemented onto a specific FPGA development platform. This thesis introduces a new processor design with compatibility in mind so that it will not be limited to a certain development platform but can be used on multiple different platforms as far as they meet the basic requirements. This processor is a single-stage processor without any pipeline implemented. The processor is used to evaluate the power efficiency of the architecture and has a unique feature to enable or disable the RISC-V Compressed (RVC) instruction subset to understand its impact on power-efficient. It is simple in architecture but still has the full capability for the RV64IC instruction set. Because of it uses RISC-V architecture, in the future, this processor can be easily expanded to adopt more RISC-V instruction subsets