More for Less : RISC, a Simple VLSI Processor Architecture

The benefits of very Large Scale Integration (VLSI) appear to mount daily. One such benefit is that due to the large number of circuits which can be fabricated on a chip and the increased memory speed, more •efficient• processor architectures have been proposed, built, and tested. Many of these architectures have arisen out of a specialized need such as the systolic array, RSA cipher chip, and the Xerox Optical Mouse chip. Other processor architectures, such as the X-Tree machine; Scheme-79 and RISC were born out of a desire to improve upon existing architectural concepts. The intent of this essay is twofold: to briefly discuss the background of VLSI and processor architectures, and to give an in-depth overview of the Reduced Instruction Set Computer (RISC). The design and development strategy, instruction features, and datapath design of RISC-I [Berkeley version] are discussed. Other RISC efforts, specifically the IBM 801 minicomputer and the MIPS machine are presented and compared to the Berkeley version. The future of RISC is addressed by a discussion of its performance and suggestions for modifications to the architecture. Because of the newness of the subject matter, most of the supporting references are from published papers found in trade magazines and journals