Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA

Stencils are a fundamental access pattern in scientific codes based on Partial Differential Equations (PDEs), ranging from weather forecasting models to geophysical simulations. Whilst efficient ways of computing stencils have been extensively researched for CPUs and GPUs, it has been done less so for FPGAs, and where it has, the focus is mainly on manual optimisation. We propose Stencil-HMLS, a multi-layered approach to automatic optimisation of stencil codes, and introduce the HLS dialect, that abstracts away important concepts for performance on FPGAs. We demonstrate an improvement of 14-100x, depending on the complexity of the code, with respect to the next best performant state-of-the-art tool. Furthermore, our approach is 14-92x more energy efficient than the next most energy efficient tool