Deriving stencil hardware accelerators from a single higher-order function

Stencil computations are array based algorithms that apply a computation to all array elements in a fixed regular pattern and can be found in many scientific and engineering applications. Parallelization of these applications becomes more and more important in order to keep up with the demand for computing power. FPGAs offer a lot of computing power but are considered hard to program. In this paper, a design methodology based on transformations of higher-order functions is introduced to facilitate this parallelization process. Using this methodology, efficient FPGA hardware is derived achieving good performance. Two architectures for heat flow computations are synthesized for an FPGA and evaluated. To show the general applicability of the design methodology, several applications have been implemented