High-performance code generation for stencil computations on GPU architectures

Stencil computations arise in many scientific computing do-mains, and often represent time-critical portions of applica-tions. There is significant interest in offloading these com-putations to high-performance devices such as GPU acceler-ators, but these architectures offer challenges for developers and compilers alike. Stencil computations in particular re-quire careful attention to off-chip memory access and the balancing of work among compute units in GPU devices. In this paper, we present a code generation scheme for stencil computations on GPU accelerators, which optimizes the code by trading an increase in the computational work-load for a decrease in the required global memory band-width. We develop compiler algorithms for automatic gen-eration of efficient, time-tiled stencil code for GPU accel-erators from a high-level description of the stencil opera-tion. We show that the code generation scheme can achieve high performance on a range of GPU architectures, includ-ing both nVidia and AMD devices