An alternative superscalar architecture with integer execution units only

Superscalar architecture resulting in aggressive performance is a proven architecture for general purpose computation. The negative side effect of aggressive performance is the need for higher number of register read/write ports to supply operands to multiple execution units; the need to resolve false data dependence and true data dependence; the need to dispatch operand ready instructions to execution units and finally retire out of order executed instructions to program order. A processor architecture is proposed in here to address at least some of the above negative side effects. This processor architecture is call LITERAL QUEUE ARCHITECTURE(LQA). In here, LITERAL has the meaning of immediate data. In LQA, opcode and operands in an instruction are treated as a self contained structured element and forms the necessary and sufficient condition for instruction execution. Sequence of instructions embedded with LITERALS are treated as elements in a QUEUE. The elements are executed with respect to time and rotated out of the QUEUE while new elements are rotated into the QUEUE