A Simple Superscalar Architecture

We present a simple technique for instruction-level parallelism and analyze its performance impact. Our processor architecture economically encodes two instructions, one ALU and one load/store, into a single 32-bit instruction word. Using an existing RISC processor design as a starting point, we detail the instruction set, the pipeline design, and scheduling techniques. Implementation should require little or no additional hardware over the scalar processor, and may require less. Simulation results show up to 13% improvement in program execution time. Corresponding author. The work described in this paper was performed at the University of Western Ontaro. y Michael Bennett is a professor in the Computer Science Department, University of Western Ontario, London, Ontario, N6A 5B7 Canada. Jan Graczyk is a graduate of UWO. z Computer Science Department, University of Waterloo, Waterloo, Ontario, N2L 3G1 Canada. 1 Introduction Many new architectures have chosen to use a dynamic app..