Hyperscalar Processor Architecture and the Preliminary Performance Evaluation

This paper describes a novel processor architecture, called hyperscalar processor architecture, which encompasses the advantages of superscalar, VLIW, and vector processor architectures and excludes their disadvantages. In brief hyperscalar is a processor, i) whose instruction size and instruction-fetch bandwidth are the same as those of superscalar, ii) whose datapath is as large as that of VLIW, iii) which provides every independent functional unit with one or more compiler-visible registers, called instruction registers, and iv) which allows the program itself to load the instruction registers with instructions fetched from the memory and to execute them as a subroutine. As compiler techniques for creating an object code placed in the instruction registers, this paper proposes pseudo vector processing and software pipelining, and further discusses several issues on applying software pipeling to hyperscalar processors. This paper evaluates the performance attainable in hyperscalar processors, and then concludes that hyperscalar processors can outperform conventional superscalar, VLIW, and vector processors in terms of cost/performance