Quantifying the Complexity of Superscalar Processors

To characterize future performance limitations of superscalar processors, the delays of key pipeline structures in superscalar processors are studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and operand bypass-ing are analyzed. Each is modeled and Spice simulated for feature sizes of 0:8m, 0:35m, and 0:18m. Performance (delay) results and trends are expressed in terms of issue width and window size. This anal-ysis indicates that window (wakeup and select) logic and operand bypass logic are likely to be the most critical in the future.