Decomposing the Load-Store Queue by Function for Power Reduction and Scalability

Because they are based on large content-addressable memories, load-store queues (LSQs) present implementation challenges in superscalar processors, especially as issue width and number of in-flight instructions are scaled. In this paper, we propose an alternate organization of an LSQ that separates the time-critical forwarding functionality from checking that loads received their correct values. Two main techniques are exploited: 1) the store forwarding logic is only accessed by those loads and stores that are likely to be involved in forwarding, and 2) the checking structure is banked by address. The result of these techniques is that a collection of small, low bandwidth structures can be substituted for the large, high bandwidth structures used in conventional designs. By our calculations, these proposed techniques reduce LSQ dynamic power by a factor of 3-5 while achieving equivalent performance. Furthermore, we explore applying these techniques to processors requiring only statistical correctness guarantees where another factor of two power reduction is achievable