Increasing FPGA Accelerators Memory Bandwidth with a Burst-Friendly Memory Layout

International audienceOffloading compute-intensive kernels to hardwareaccelerators relies on the large degree of parallelism offered bythese platforms. However, the effective bandwidth of the memoryinterface often causes a bottleneck, hindering the accelerator’seffective performance. Techniques enabling data reuse, such astiling, lower the pressure on memory traffic but still often leave the accelerators I/O-bound. A further increase in effectivebandwidth is possible by using burst rather than element-wiseaccesses, provided the data is contiguous in memory.In this paper, we propose a memory allocation technique,and provide a proof-of-concept source-to-source compiler pass,that enables such burst transfers by modifying the data layoutin external memory. We assess how this technique pushes up the memory throughput, leaving room for exploiting additional parallelism, for a minimal logic overhead