Electronic Systems

High Level Synthesis tools have reduced accelerator design time. How-ever, a complex scaling problem that remains is the data transfer bottle-neck. Accelerators require huge amounts of data and are often limited by interconnect resources. Local buffers can reduce communication by ex-ploiting data reuse, but the data access order has a substantial impact on the amount of reuse that can be utilized. With loop transformations such as interchange and tiling the data access order can be modified. How-ever, for real applications the design space is huge, finding the best set of transformations is often intractable. Therefore, we present a new method-ology that minimizes the data transfer by loop interchange and tiling. In contrast to other methods we take inter-tile reuse and loop bounds into account. For real-world applications we show buffer size trade-offs that can give speedups up to 14x, alternatively these can reduce the required FPGA resources substantially