A Comparative Study of Chisel for FPGA Design

This paper presents the results of a comparative study conducted into designing with the Chisel hardware construction language against the Verilog hardware description language across a range of standard-library and bespoke FPGA design components including an N-bit FIFO, a round-robin arbiter and a complex, scalable arbiter. Comparison metrics such as maximum operating frequency, silicon area, design flow run-time, source-code density and maintainability, simulation run-time and speed of coding are employed to evaluate the merits of designing with Chisel. Each component is implemented with a deep low-level hardware understanding with an aim to evaluate the merits of designing with Chisel from a hardware designers\u27 perspective. The authors discover Chisel\u27s merits for realising synthesizable repetitive designs such as in SoC development, experiencing the benefits of Chisel\u27s object-oriented background in enhancing code maintainability and scalability, and implementation efficiency. However, the authors foresee that Chisel will compliment rather than replace traditional HDLs for RTL design applications due to its limitations in terms of behavioural modelling