Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification

Chisel is a hardware design method that uses Scala programming language, and exploits many useful features of Scala like object-oriented programming and functional programming. By comparing two equivalent RISC-V core designs, one implemented using each hand-written Verilog code and one using Chisel, this paper compares manual Verilog coding and Chisel coding. The comparison metrics are source-code density, area of synthesized hardware, and RTL simulation run-Time. As a result, Chisel is proved to be more productive than Verilog.1