An approach for investigating design and tuning performance of embedded systems

Showing the internal behavior of a computer and the didactic path which conducts to the final design of an embedded system is often a difficult task, without adequate tools. Classical approaches may skip details of the underlaying architecture which can be fundamental to meet particular timing or consumption requirements. We propose an approach based on an environment which allows a high level of detail to be simulated, including cache, memory and I/O subsystem