Architectural Exploration and Optimization of Local Memory in Embedded Systems

Embedded processor-based systems allow for the tai-loring of the on-chip memory architecture based on application-specific requirements. We present an analytical strategy for exploring the on-chip memory architecture for a given application, based on a memory performance esti-mation scheme. The analytical technique has the important advantage of enabling a fast evaluation of candidate mem-ory architectures in the early stages of system design. Our experiments demonstrate that our estimations closely follow the actual simulated performance, at significantly reduced run times. 1