Synthesis for dependability of finite state machines

CAD Tools are more and more used by designers, and integrated circuits synthesized using these tools are now often used in critical applications. These tools classically don't take into account the dependability constraints. So we developed the ASYL-SdF tool and we propose some solutions more difficult to implement than those used during manual implementations but more efficient in terms of silicon area overhead for the same reliability. This paper deals with finite state machines (FSMs) implemented to control all the operations performed by the circuit and fault tolerance in these FSMs. The comparison of the results obtained with five synthesis flows shows the interest of the use of single-error correcting codes instead of the classical triplication and voting scheme (TMR) to achieve fault tolerance