Generating finite state machines from SystemC

SystemC is a system level language proposed to raise the abstraction level for embedded systems design and verifica-tion. In this paper, we propose to generate Finite State Ma-chines (FSM) from SystemC designs using two algorithms originally proposed for the generation of FSM from Ab-stract State Machines (ASM). This proposal enables the in-tegration of SystemC with existing tools for test case gen-eration from FSM. Hence, enabling two important appli-cations: (1) using the FSM graph structure to produce test suites allowing functional testing of SystemC designs; and (2) performing conformance testing, where the FSM serves as a precise model of the observable behavior of the sys-tem used to validate lower abstraction levels of the design (e.g., Register Transfer Level (RTL)). 1