We have developed a two-step anisotropic etching process to fabricate thin silicon membranes, used to study supercurrent transport in semiconductor coupled weak links. The process uses a shallow BF2+ implantation, and permits easy control of membrane thickness less-than-or-equal-to 100 nm. Preliminary measurements on membrane-based Nb-Si-Nb junctions reveal the simultaneous occurrence of tunnel behavior and Josephson coupling
We present the development of a novel, UHV-compatible device fabrication strategy for the realisatio...
We describe two process steps in an STM-based fabrication technology for nanoelectronic devices. Fir...
Membranes of micrometer lateral sizes and nanometer thickness are nowadays routinely fabricated thro...
We have developed a two-step anisotropic etching process to fabricate thin silicon membranes, used t...
We have developed a two-step anisotropic etching process to fabricate thin silicon membranes, used t...
We have developed a two-step anisotropic etching process to fabricate thin silicon membranes, used t...
We have developed a two-step anisotropic etching process to fabricate thin silicon membranes, used t...
An enhancement of the zero-voltage conductance of a niobium-silicon junction is found at very low te...
An enhancement of the zero-voltage conductance of a niobium-silicon junction is found at very low te...
An enhancement of the zero-voltage conductance of a niobium-silicon junction is found at very low te...
Vertically oriented, bandgap engineered silicon double tunnel junction nanopillars were fabricated a...
Vertically oriented, bandgap engineered silicon double tunnel junction nanopillars were fabricated a...
Low resistivity, near-surface doping in silicon represents a formidable challenge for both the micro...
We describe two process steps in an STM-based fabrication technology for nanoelectronic devices. Fir...
We describe two process steps in an STM-based fabrication technology for nanoelectronic devices. Fir...
We present the development of a novel, UHV-compatible device fabrication strategy for the realisatio...
We describe two process steps in an STM-based fabrication technology for nanoelectronic devices. Fir...
Membranes of micrometer lateral sizes and nanometer thickness are nowadays routinely fabricated thro...
We have developed a two-step anisotropic etching process to fabricate thin silicon membranes, used t...
We have developed a two-step anisotropic etching process to fabricate thin silicon membranes, used t...
We have developed a two-step anisotropic etching process to fabricate thin silicon membranes, used t...
We have developed a two-step anisotropic etching process to fabricate thin silicon membranes, used t...
An enhancement of the zero-voltage conductance of a niobium-silicon junction is found at very low te...
An enhancement of the zero-voltage conductance of a niobium-silicon junction is found at very low te...
An enhancement of the zero-voltage conductance of a niobium-silicon junction is found at very low te...
Vertically oriented, bandgap engineered silicon double tunnel junction nanopillars were fabricated a...
Vertically oriented, bandgap engineered silicon double tunnel junction nanopillars were fabricated a...
Low resistivity, near-surface doping in silicon represents a formidable challenge for both the micro...
We describe two process steps in an STM-based fabrication technology for nanoelectronic devices. Fir...
We describe two process steps in an STM-based fabrication technology for nanoelectronic devices. Fir...
We present the development of a novel, UHV-compatible device fabrication strategy for the realisatio...
We describe two process steps in an STM-based fabrication technology for nanoelectronic devices. Fir...
Membranes of micrometer lateral sizes and nanometer thickness are nowadays routinely fabricated thro...