A flexible floating-point logarithm for reconfigurable computers

The advent of reconfigurable co-processors based on field-programmable gate arrays has renewed interest in hardware architectures for elementary functions. This article studies operators for the logarithm function in the context of this target technology. An old algorithm is generalized, fine-tuned and implemented as an architecture generator, exposing a wide range of trade-offs between resources (memory, logic and multipliers) and performance (frequency and pipeline depth). A single pipelined operator computes five times more double-precision floating-point logarithms per second than a high-end processor core, while consuming only a few percents of the resources of a high-end FPGA. This generator is available under the LGPL as part of the FloPoCo project