Synthesizing variations tolerant clock network using cross links insertion

Clock distribution network (CDN) synthesis is one of the most fundamental CAD problems, and with the ever increasing performance demands of today\u27s VLSI chips, this problem is getting even more difficult. Moreover, as one of the largest and fastest switching nets in the design, the CDN has a great influence on the overall performance of the chip. However, with the scaling of the VLSI technology, the power supply and wire width variations tend to have a significant impact on the performance of the CDN. Generally, the sequential elements that are related, for example one element feeding data to the other, are placed closer to each other. The clock skew between any pair of sequential elements that are separated by less than a specified distance is defined as Local Clock Skew (LCS). The aim of this thesis is to synthesize a low power clock tree that have low Maximum local clock skew (MLCS) in the entire design, even in the presence of power supply and interconnect-width variations. Cross links inserted in a buffered clock tree has been shown to be effective in reducing the skew variations. In earlier work cross links are inserted between the sinks of DC-connected trees. In this work we propose a link insertion scheme that inserts cross links at higher level internal nodes in a clock tree. In addition to reducing the skew variability, the proposed work also reduces the total cross link length. Our work also improves the correlation of sink delays as the sinks in a subtree have the similar path lengths to the cross link. Monte-Carlo simulations on the ISPD-2010 benchmarks showed that our work could handle the variations effectively. In addition to meeting all the design constraints, the solutions produced by our approach have on an average 30% lower capacitance than the least capacitance obtained by the top three teams in the ISPD-2010 design contest