Buffered clock tree for high quality IC design

In ultra-deep submicron VLSI designs, clock network layout plays an increasingly important role on determin-ing circuit quality indicated by timing, power consumption, cost, power supply noise and tolerance to process varia-tions. In this paper, a clock tree routing algorithm is pro-posed to achieve any prescribed non-zero skews which are useful in reducing clock cycle time [1], suppressing power supply noise [2] and improving tolerance to process varia-tions [3]. The interactions among skew targets, sink loca-tion proximities and capacitive load balance are analyzed. Based on this analysis, a maximum delay-target ordering merging scheme is suggested to minimize wire and buffer area which imply cost, power consumption and vulnerabil-ity to process variations. During the clock routing, buffers are inserted simultaneously to facilitate a proper skew rate level and reduce wire snaking. The proposed algorithm is simple and fast for practical applications. Experimental re-sults on benchmark circuits show that the proposed algo-rithm can reduce the total wire and buffer capacitance by 60 % over an extension of existing zero skew routing method.