Synthesis of Low Power Clock Trees for handling Variations

In synchronous circuit design, data is processed in an orderly fashion with the help of sequential elements like flip-flops. A periodic signal, called the clock signal, is delivered to these sequential elements to achieve synchronization. The control of the arrival times of clock signal to these sequential elements is critical for the correct operation of the system. The difference in the arrival times of clock signal between any pair of sequential elements is defined as the clock skew. Minimization of clock skew, especially in the presence of process and power-supply variations, is an important problem in the design of Very Large Scale Integration (VLSI) circuits. Since clock networks are actively switching circuits that consume significant amount of power in VLSI design, it is necessary to construct low power clock distribution networks while satisfying clock skew requirements. International Symposium on Physical Design (ISPD) organized contests in the years 2009 and 2010 on Clock Network Synthesis with benchmark circuits from real industrial designs. Generally, the sequential elements that are related, for example one element feeding data to the other, are placed close to each other. The clock skew between any pair of sequential elements that are separated by less than a specified distance is defined as Local Clock Skew (LCS). The aim of this thesis is to construct low power clock trees that have low Maximum local clock skew (MLCS) in the entire design, even in the presence of power supply and interconnect-width variations. The clock router has been tested on the ISPD2010 contest benchmarks, all of which have stringent MLCS constraints. The results of the study show that clock tree solutions, as opposed to the costlier clock mesh solutions, can effectively handle variations even when certain stringent MLCS constraints are imposed for these benchmark circuits