Improving the robustness of high-speed clock distribution networks

As the semiconductor technology advances, minimum feature sizes are reduced and clock speeds are increased. Although these changes result in higher performance circuits, their tolerance to errors are reduced, especially when supply voltages are scaled down. Some of the errors are caused by operating environment variations that are introduced during circuit operation and some errors are caused by variations due to manufacturing processes. Failure to account for these variations during the design stage may lead to increased yield loss and decreased reliability in circuits. Clock distribution networks are made of long interconnects and may span the entire circuit, since their function is to synchronize data flow in the circuit. High clock speeds and large capacitances translates to large amounts of current drawn from the power and ground supply lines during the clock switching events. This may introduce power noise, or environmental variations, to the circuit and reduces the reliability of the circuit. Meanwhile, the clock distribution networks are affected by process variations. In this work, we propose a method to suppress the power noise due to simultaneous switching events. We also focus on the effects of parameter variations on clock distribution networks and propose synthesis algorithms to increase the robustness of clock distribution networks. Both worst-case and statistical variation models are explored